/*
 * Copyright (c) 2016, 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* Auxiliary structs for architecture traits. */

#ifndef __ARCH_COMMON_TRAITS_HH__
#define __ARCH_COMMON_TRAITS_HH__

#include "arch/generic/isa.hh"
#include "arch/types.hh"
#include "enums/VecRegRenameMode.hh"

/** Helper structure to get the vector register mode for a given ISA.
 * This way we implement a default 'full' mode, and only those ISA that care
 * have to actually specialise the template to forward the call to the
 * appropriate member of the ISA.
 */
template <typename ISA>
struct RenameMode
{
    static Enums::VecRegRenameMode init(const BaseISA*) { return Enums::Full; }

    static Enums::VecRegRenameMode
    mode(const TheISA::PCState&)
    { return Enums::Full; }

    /**
     * Compare the initial rename mode of two instances of the ISA.
     * Result is true by definition, as the default mode is Full.
     * */
    static bool equalsInit(const BaseISA*, const BaseISA*) { return true; }
};

#endif /* __ARCH_COMMON_TRAITS_HH__ */
